Embedded computer systems can have many interrupts occurring in a brief time interval. In such systems, latency of interrupt processing can be very important. Latency is the interval between the time that an interrupting device asserts an interrupt signal and the time that a processor executes code to handle the interrupt. A short interrupt latency interval is desirable. In some application domains, a small variation of interrupt latencies is also desirable. A small variation in possible latency interval lengths results in a greater predictability of when a processor will begin executing code to process the interrupt. For example, a computer system can have a short average interrupt latency, but for a very small fraction of interrupt events the latency can be so long that an interrupt is not handled properly and the system fails.
Hierarchical memory systems, such as those including a cache sub-system, can affect interrupt latencies in some systems. While cache memories generally improve system performance by allowing code and data to be accessed from fast cache memories instead of slower memory, loading cache memories can introduce unpredictable delays. A cache memory can be organized into cache lines, and the system designed such that one a cache sub-system begins filling a cache line it must complete filling the cache line before beginning another operation. When the next operation to be performed is providing a memory word to a processor in order for the processor to begin executing interrupt handler code, the latency of interrupt processing by the processor can be affected. If the request to provide a word occurs just as the cache sub-system begins filling a cache line, the processor can be forced to wait until the current cache line fill is completed before beginning a cache search or for the interrupt handler code.
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